High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands

We present a new methodology for designing modulo 2"+1 adders with operands in the diminished-one number system. The proposed methodology leads lo parallel-prejix adder implementations. Both an analytical model and V U 1 implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate that the proposed parallel-prefu adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2" and modulo 2"-1 adders.